1. Field of the Invention
The present invention primarily relates to an electronic matrix array and more particularly to distributed arrays, especially deposited, distributed arrays, such as distributed transistor matrix arrays and distributed diode matrix arrays. The present invention further relates to improved read only memory (ROM) devices, electronically erasable programmable read only memory (EEPROM) devices, programmable read only memory (PROM) devices, field programmable logic arrays, and flat panel displays wherein the distributed diode matrix array facilitates isolation and addressing. The present invention allows such structures to be made with substantially greater packing densities than prior art arrays and with reduced processing steps and lithography control tolerances. Of great importance is the fact that these structures can be made in accordance with the present invention on substrates much larger than previously possible to provide substantially increased data storage, logic operations, or flat panel display areas. The diode matrix of the present invention is formed from amorphous alloys, including silicon, deposited onto large area substrates. To that end, reference can be made to the disclosure in U.S. Pat. No. 4,217,374 to Stanford R. Ovskinsky and Masatsugu Izu entitled: AMORPHOUS SEMICONDUCTORS EQUIVALENT TO CRYSTALLINE SEMICONDUCTORS and U.S. Pat. No. 4,226,898 Stanford R. Ovshinsky and Arun Madan, of the same title.
2. Description of the Prior Art
Silicon is the basis of the huge crystalline semiconductor industry and is the material which is utilized in substantially all the commercial integrated circuits now produced. When crystalline semiconductor technology reached a commercial state, it became the foundation of the present huge semiconductor device manufacturing industry. This was due to the ability of the scientist to grow substantially defect-free germanium and, particularly, silicon crystals, and then turn them into extrinsic materials with p-type and n-type conductivity regions therein. This was accomplished by diffusing into such crystalline material parts per million of donor (n) or acceptor (p) dopant materials introduced as substitutional impurities into the substantially pure crystalline materials, to increase their electrical conductivity and to control their being either a p or n conduction type.
The semiconductor fabrication processes for making p-n junction crystals involve extremely complex, time consuming, and expensive procedures as well as high processing temperatures. Thus, these crystalline materials used in rectifying and other current control devices are produced under very carefully controlled conditions by growing individual single silicon or germanium crystals, and where p-n junctions are required, by doping such single crystals with extremely small and critical amounts of dopants. These crystal growing processes produce relatively small crystal wafers upon which the integrated memory circuits are formed.
In conventional crystalline integrated circuit technology the small area crystal wafer limits the overall size of the integrated circuits which can be formed thereon. In applications requiring large scale areas, such as the display technology, the crystal wafers cannot be manufactured with as large areas as required or desired. The devices are formed, at least in part, by diffusing p or n-type dopants into the substrate. Further, each device is formed between isolation channels which are diffused into the substrate and interconnected on each level of metalization by horizontally spaced conductors. Packing density (the number of devices per unit area of wafer surface) is thereby limited on the surface of the silicon wafers because conductors cannot be placed below the diffused junction areas. Costs are increased and yields decreased by the many lithographic steps required.
Further, the packing density is extremely important because the cell size is exponentially related to the cost of each device. For instance, a decrease in die size by a factor of two results in a decrease in cost on the order of a factor of six. A conventional crystalline ROM utilizing two micron lithography has a bipolar cell size of about 0.3 to 0.5 mil.sup.2 or MOS cell size of about 0.2 to 0.3 mil.sup.2.
In summary, crystal silicon rectifier and integrated circuit structures have to be spread horizontally across their crystalline wafer, they require many sequential processing and aligning steps, large amounts of material, high processing temperatures, are producible only on relatively small area wafers and are expensive and time consuming to produce. Devices based upon amorphous silicon can eliminate these crystal silicon disadvantages. Amorphous silicon can be made faster, easier, at lower temperatures and in larger areas than can crystal silicon and it can be deposited in layers on top of conductors as well as below conductors.
Accordingly, a considerable effort has been made to develop processes for readily depositing amorphous semiconductor alloys or films each of which can encompass relatively large areas, if desired, limited only by the size of the deposition equipment, and which could be doped to form p-type and n-type materials to form p-n junction rectifiers and devices superior in cost and/or operation to those produced by their crystalline counterparts. For many years such work was substantially unproductive. This was because amorphous silicon or germanium (Group IV) are normally four-fold coordinated and were found to have microvoids and dangling bonds and other defects with produced a high density of localized states in the energy gap thereof. The presence of a high density of localized states in the energy gap of amorphous silicon and germanium semiconductor films resulted in such films not being successfully doped or otherwise modified to shift the Fermi level close to the conduction or valence bands. The inability to shift the Fermi level made them unsuitable for making p-n junction rectifiers and other current control device applications.
In an attempt to minimize the aforementioned problems involved with amorphous silicon and germanium, W. E. Spear and P. G. Le Comber of Carnegie Laboratory of Physics, University of Dundee, in Dundee, Scotland did work on "Substitutional Doping of Amorphous Silicon", as reported in a paper published in Solid State Communications, Vol 17, pp. 1193-1196, 1975. Spear, et al's work was directed toward the end of reducing the localized states in the enrgy gap in amorphous silicon and germanium to make the same approximate more closely intrinsic crystalline silicon or germanium, and of substitutionally doping the amorphous materials and suitable classic dopants, as in doping crystalline materials, to make them extrinsic semiconductors, i.e., of p or n conduction types.
The reduction of the localized states was accomplished by glow discharge deposition of amorphous silicon films wherein a gas of silane (SiH.sub.4) was passed through a reaction tube where the gas was decomposed by a r.f. glow discharge and deposited on a substrate at a substrate temperature of about 500.degree.-600.degree. K. (227.degree.-327.degree. C.). The material so deposited on the substrate was an intrinsic amorphous material consisting of silicon and hydrogen. To produce a doped amorphous material a gas of phosphine (PH.sub.3) for n-type conduction or a gas of diborane B.sub.2 H.sub.6) for p-type conduction were premixed with the silane gas and passed through the glow discharge reaction tube under the same operating conditions. The gaseous concentration of the dopants used was between about 5.times.10.sup.-6 and 10.sup.-2 parts per volume. The material so deposited included supposedly substitutional phosphorous or boron dopant and was shown to be extrinsic and of n or p conduction type.
While it was not known by these researchers, it is now known by the work of others that the hydrogen in the silane combines at an optimum temperature with many of the dangling bonds of the silicon during the glow discharge deposition to substantially reduce the density of the localized states in the energy gap toward the end of making the electronic properties of the amorphous material approximate more nearly those of the corresponding crystalline material.
Greatly improved amorphous silicon alloys having significantly reduced concentrations of localized states in the energy gaps thereof and high quality electronic properties have been prepared by glow discharge as fully described in U.S. Pat. No. 4,226,898, Amorphous Semiconductors Equivalent to Crystalline Semiconductors, to Stanford R. Ovshinsky and Arun Madan which issued Oct. 7, 1980, and by vapor deposition as fully described in U.S. Pat. No. 4,217,374, to Stanford R. Ovshinsky and Masatsugu Izu, which issued on Aug. 12, 1980, under the same title. As disclosed in these patents, fluorine is introduced into the amorphous silicon semiconductor alloy to substantially reduce the density of localized states therein. Activated fluorine especially readily diffuses into and bonds to the amorphous silicon in the amorphous body to substantially decrease the density of localized defect states therein, because the small size of the fluorine atoms enables them to be readily introduced into the amorphous body. The fluorine bonds to the dangling bonds of the silicon and forms what is believed to be a partially ionic stable bond with flexible bonding angles, which results in a more stable and more efficient compensation or alteration than is formed by hydrogen and other compensating or altering agents. Fluorine also combines in a preferable manner with silicon and hydrogen, utilizing the hydrogen in a more desirable manner, since hydrogen has several bonding options. Without fluorine, hydrogen may not bond in a desirable manner in the material, causing extra defect states in the band gap as well as in the material itself. Therefore, fluorine is considered to be a more efficient compensating or altering element than hydrogen when employed alone or with hydrogen because of its high reactivity, specificity in chemical bonding, and high electro-negativity.
As an example, compensation may be achieved with fluorine alone or in combination with hydrogen with the addition of these element(s) in very small quantities (e.g., fractions of one atomic percent). However, the amounts of fluorine and hydrogen most desirably used are much greater than such small percentages so as to form a silicon-hydrogen-fluorine alloy. Such alloying amounts of fluorine and hydrogen may, for example, be in the range of 1 to 5 percent or greater. It is believed that the alloy so formed has a lower density of defect states in the energy gap than that achieved by the mere neutralization of dangling bonds and similar defect states.
Heretofore various semiconductor materials, both crystalline and amorphous, have been proposed for utilization in rectifying type devices such as a diode. As is described in my commonly assigned, copending U.S. application Ser. No. 458,919, and as will be described in greater detail hereinafter, the distributed diode array of the present invention is formed from amorphous alloys including silicon as for example disclosed in the applications identified above. The distributed diode array of the present invention can be utilized in the ROM, EEPROM and PROM devices of the present invention as well as in the field programmable arrays and flat panel displays of the present invention.
Heretofore various memory systems have been proposed which are divided into several types. One type is the serial type where the information in the memory system is obtained serially and where the read time for reading a particular bit of information in the memory is dependent upon where it is located in the memory. This results in long read times for obtaining the information from memory. Such types of memory systems include memory devices including a magnetic tape or a magnetic disc including the so-called floppy disc and magnetic "bubble memory" devices. While the storage information in "bubble" type memory devices potentially reduces the size and cost of memory systems and provides high information packing densities, i.e., small center-to-center distance between adjacent memory regions where the bits of information are stored, such "bubble" systems are limited to serial reading of information and do not provide for fast read, random access to the stored information.
Also, heretofore, short term data storage has been provided by random access memory (RAM) devices including transistors or capacitors at the intersections of X and Y axis conductors. Such a memory device can be set in one of two operational states. These memory devices provide a fairly high packing density, i.e., a small center-to-center distance between memory locations. A major disadvantage is that such devices are volatile since they must be continually supplied with a voltage if they are to retain their stored data. Such short term data storage devices are often referred to as volatile fast read and write memory systems.
A fast read non-volatile memory system is the read only memory (ROM) which uses transistors and rectifiers formed in semiconductor substrates with permanently open contact points or permanently closed contact points in an x-y array for storage of bits of information. Such a ROM system is typically mask-programmed during the manufacture thereof and has a fast read time and a relatively high packing density as well as being non-volatile. However, the obvious disadvantage of such a ROM system is that the data stored cannot be altered and has to be built in at the factory. Accordingly, ROM devices are made-to-order for applications involving storing of the basic operating program of a data processor or other non-altered information.
Another memory system used is a programmable read only memory (PROM) system which can be programmed once by the user and remains in that state. Once it is programmed a PROM system will operate identically to a ROM system of the same configuration.
The most commonly used PROM system incorporates fuse links positioned at each intersection of an X-Y matrix of conductors. The storage of information (logic one or logic zero) is obtained by blowing the fuse links in a given predetermined pattern. Such fuse links extend laterally on a single crystal substrate instead of vertically between crossover conductors and, as a result, such fuse links necessarily require a large area. The area of a typical memory cell or region utilizing a fuse link is about 1 to 1.6 mil.sup.2.
The current needed to blow the fuse link for programming is quite high because of the necessity of completely blowing out the fuse link and because of the inherently high conductivity of the material of the fuse link. Typical currents are 50 milliamps and the power required is approximately 250 to 400 milliwatts. Also, the fuse link which is a narrow portion of a conductor deposited on a substrate, must have a precise dimension to ensure the complete and programmable blow out thereof. In this respect, photolitography and etching techniques required to fabricate such a fuse link require that such a fuse link be made with very critical tolerances.
Another major problem with fuse link type PROM devices is that the small gap in the blown fuse can become closed with accumulation of conductive material remaining adjacent to the gap by diffusion or otherwise.
The fuse link technology also has been utilized in field programmable logic arrays, redundant memory arrays, gate arrays and die interconnect arrays. Field programmable logic arrays are utilized to provide options for the integrated circuit user between the standard high volume, low cost logic arrays and the very expensive handcrafted custom designed integrated circuits. These arrays allow a user to program the low cost array for the users specific application at a substantially reduced cost from the cost of a custom application circuit.
Heretofore it has also been proposed to provide an EEPROM (electrically erasible programmable read only memory) device, a vertically disposed memory region or cell in a memory circuit which is vertically coupled at and between an upper Y axis conductor and a lower X axis conductor in a memory matrix. Such an EEPROM system provides a relatively high packing density. Examples of such EEPROM's are disclosed in the following patents:
______________________________________ U.S. Pat. No. PATENTEE ______________________________________ 3,571,809 Nelson 3,573,757 Adams 3,629,863 Neale 3,699,543 Neale 3,846,767 Cohen 3,886,577 Buckley 3,875,566 Helbers 3,877,049 Buckley 3,922,648 Buckley 3,980,505 Buckley 4,177,475 Holmberg ______________________________________
Specific reference is made to the U.S. Pat. No. 3,699,543 to Neale directed to: COMBINATION FILM DEPOSITED SWITCH UNIT AND INTEGRATED CIRCUIT and to U.S. Pat. No. 4,177,475 to Holmberg directed to: HIGH TEMPERATURE AMORPHOUS MEMORY DEVICE FOR AN ELECTRICALLY ALTERABLE READ ONLY MEMORY.
These references illustrate EEPROM devices including a matrix of X and Y axis conductors where a memory circuit, including a memory region and an isolating device is located at each crossover point and extends generally perpendicularly to the crossover conductors thereby to provide a relatively high packing density.
The memory region utilized in such EEPROM devices have typically been formed of a tellurium-based chalcogenide material and more specifically an amorphous material such as amorphous germanium and tellurium. Other materials which have rather highly reversible memory regions include a Ge.sub.a Te.sub.b wherein a is between 5 and 70 atomic percent and b is between 30 and 95 atomic percent, based on total germanium and tellurium. Some of these materials also include other elements in various percentages from 0 to 40 in atomic percent such as antimony, bismuth, arsenic, sulfur and/or selenium.
Heretofore it has also been known to provide isolating devices which are coupled in series with a memory region or cell at the intersections of orthogonal conductors, such isolating devices typically having been formed by diffusing various dopant materials into a single crystal silicon substrate to form a rectifier, transistor, or MOS device, e.g., a field effect transistor. Such a diffusion process requires horizontally spaced x-y conductors and results in lateral diffusion of the doped material into the substrate material. As a result, the cell packing densities of such prior memory systems have been limited by the number of horizontal metal lines and by the degree of lateral diffusion of the dopant materials and by the margin of error required for mask alignment.
Heretofore an all thin film EEPROM device has been proposed and is disclosed in U.S. Pat. No. 3,629,863, referred to above. The all thin film memory circuit disclosed in U.S. Pat. No. 3,629,863 utilized deposited film bidirectional threshold type isolating devices.
The devices herein utilized for each isolating device a diode which is a unidirectional isolating device and which provides isolation by a high impedance p-i-n configuration in one direction to current flow thereby to provide very high OFF resistance.
It has been proposed to form a p-n junction by vacuum depositing, either an n or p-type amorphous semiconductor film on an oppositely doped silicon chip substrate. In this respect, reference is made to U.S. Pat. No. 4,062,034 which discloses such a thin film transistor having a p-n junction. However, it has not been previously proposed to use a thin film deposited amorphous semiconductor film for forming p-i-n isolating devices in a programmable array.